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Instruction set architecture
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191	EN164: Design of Computing Systems Lecture 20: Processor / ILP 1 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:54 Parallel computing Classes of computers Central processing unit Superscalar Very long instruction word Hazard Instruction set Slot NOP Computer architecture Computing Computer engineering
192	Exploiting Locality to Improve Circuit-level Timing Speculation Jing Xin, Northwestern University and Russ Joseph, Northwestern University Abstract—Circuit-level timing speculation has been proposed as a technique to r Add to Reading List Source URL: users.eecs.northwestern.edu Language: English - Date: 2010-04-13 16:41:18 Central processing unit Computer memory Instruction set architectures CPU cache Cache Microarchitecture Intel Core DEC Alpha Computer architecture Computer hardware Computer engineering
193	Version 1 Open The Hex 8 Architecture David May: February 21, 2014 Add to Reading List Source URL: www.cs.bris.ac.uk Language: English - Date: 2014-02-21 06:51:57 Computing Instruction set architectures Central processing unit Instruction set Pointer
194	Symantec PGP Cryptographic Engine FIPSSecurity Policy Add to Reading List Source URL: csrc.nist.gov Language: English - Date: 2015-05-21 10:19:50 Advanced Encryption Standard AES instruction set X86 architecture FIPS 140-2 Cryptographic hash function FIPS 140 Key Wrap Crypto++ Pretty Good Privacy Cryptography Cryptography standards Cryptographic software
195	Version 1.0 Concurrent/Parallel Processing David May: April 9, 2014 Introduction Add to Reading List Source URL: www.cs.bris.ac.uk Language: English - Date: 2014-04-09 06:19:05 Central processing unit Parallel computing Classes of computers Microprocessors CPU cache Superscalar Cell Instruction set Branch predictor Computer architecture Computing Computer hardware
196	KCoFI: Complete Control-Flow Integrity for Commodity Operating System Kernels John Criswell, Nathan Dautenhahn, and Vikram Adve Department of Computer Science University of Illinois at Urbana-Champaign Email: {criswell,d Add to Reading List Source URL: sva.cs.illinois.edu Language: English - Date: 2014-03-30 11:43:41 Process Instruction set architectures Interrupt handler Kernel Operating system Thread Interrupt flag INT Ring Computer architecture Interrupts X86 instructions
197	Version 1.0 X and Hex David May: May 6, 2014 The X Language Add to Reading List Source URL: www.cs.bris.ac.uk Language: English - Date: 2014-05-06 09:48:01 Algebra Machine code Mathematical notation Operand Logical connective Instruction set DEC Alpha IJVM PILOT Computer architecture Computing Instruction set architectures
198	EXTWIFI + EVK Quick Start Guide External Software Framework with AVR Studio 5 1 Introduction Add to Reading List Source URL: www.hdwireless.se Language: English - Date: 2015-03-24 12:56:52 Microcontrollers Instruction set architectures AVR32 Embedded systems Build automation Compiling tools Atmel Make Joint Test Action Group Computer architecture Computing Electronics
199	The Progress of Computing William D. Nordhaus1 Yale University and the NBER August 30, 2001 version 4.4 __________________________________________________ Add to Reading List Source URL: www.econ.yale.edu Language: English - Date: 2001-08-30 14:19:28 Instruction set architectures Central processing unit Computer performance Instructions per second Dhrystone MIPS architecture Benchmark VAX Computer Computer architecture Computing Computer hardware
200	KVM on Embedded Power Architecture Platforms Stuart Yoder Software Architect, Freescale Semiconductor Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service nam Add to Reading List Source URL: kvm.et.redhat.com Language: English - Date: 2011-08-12 14:30:59 Instruction set architectures Motorola QorIQ Multi-core processor Power.org PowerQUICC PowerPC e6500 Computer architecture Freescale Semiconductor Power Architecture

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